In the ever-evolving landscape of semiconductor technology, South Korea’s SK Hynix has carved a niche for itself, particularly in the realm of NAND and DRAM memory chipsFor a long time, it has found itself trailing behind the formidable competition posed by Samsung, a powerhouse that has held a dominant position in this sectorTraditionally, Samsung's lead in both technology and market share has been a significant hurdle for SK HynixHowever, recent developments suggest that this competitive landscape is on the verge of a transformation.

A report from Business Korea at the end of October highlighted a remarkable milestone for SK Hynix: its annual operating profit from semiconductor operations is set to outstrip that of Samsung for the first time, owed largely to its success in High Bandwidth Memory (HBM). This change is indicative of a new era in the global semiconductor industry, suggesting a shift in the traditional hierarchies that have long favored Samsung.

Yet, Samsung's territory is under new threatThe NAND market, in which Samsung has historically been the leader, is now seeing SK Hynix make a significant impactBy the second quarter of 2024, reports indicate that Samsung will command a 36.9% share of the NAND marketIn contrast, SK Hynix's share, including contributions from Solidigm, has surged from 11.7% in 2020 to an impressive 22.5% within the same time frameIf current trends continue, it is projected that SK Hynix's market share could exceed 20% for the first time in 2024, heralding a new phase of competition.

In this context, SK Hynix has launched an ambitious product aimed directly at SamsungThe introduction of its new 321-layer triple-level cell (TLC) NAND flash is a striking developmentAs of late last month, SK Hynix announced that it has officially surpassed Samsung, becoming the first company in the industry to mass-produce NAND chips with this number of layersThis achievement is set to deliver significant enhancements in memory capacity at competitive prices.

SK Hynix’s newly unveiled 1 terabit 4D NAND chip exemplifies this innovation, setting a new industry benchmark

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This feat follows closely on the heels of its successful launch of 238-layer NAND, showcasing a rapid stride in technology advancementThe implications of the 321-layer chip are profound; it can dramatically enhance storage density for both consumer and enterprise solid-state drives (SSDs).

Moreover, densely stacked chips may lead to substantially reduced prices for SSDs exceeding 100TB in capacityThis specific type of NAND will prove critically important for high-demand applications such as Artificial Intelligence (AI) data centers, where efficient and high-performance storage solutions are a necessityThe advancement of this NAND technology will likely also benefit other applications that require energy-efficient storage solutions.

To achieve the remarkable feat of fitting over 300 layers into a single NAND chip, SK Hynix has utilized an innovative manufacturing techniqueTheir novel “Three Plugs” technology optimizes electrical connections, allowing for the simultaneous connection of three storage layers through vertical channelsThis technique not only enhances manufacturing efficiency but also employs low-stress materials equipped with automated alignment correction features to keep production seamless.

The challenge of connecting multiple layers comes with its own set of complications, particularly concerning stress and alignment issuesTo address these challenges, SK Hynix has developed low-stress materials and automated alignment technology, ensuring orderly processes during manufacturingWith an impressive 59% increase in production efficiency when utilizing the same platform as previous 238-layer NAND models, SK Hynix has set a new standard in the industryComparatively, the new 321-layer chips exhibit a 12% boost in data transfer speed, a 13% increase in read speed, and more than 10% improvement in energy efficiency relative to their predecessors.

The company plans to gradually expand its 321-layer product range, particularly targeting the burgeoning AI sector that demands low power consumption combined with high performance

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According to Jungdal Choi, the head of NAND development at SK Hynix, this advancement positions the company closer to leading the AI storage market, where solid-state drives (SSDs) designed for AI data centers will play a pivotal roleChoi emphasizes that SK Hynix is advancing towards becoming a comprehensive AI memory provider by expanding its offerings in ultra-high-performance NAND alongside its HBM-driven DRAM sector.

Despite these advances, SK Hynix still trails Samsung in market shareHowever, its leadership in vertical stacking technologies hints at a potential seismic shift in the NAND market dynamicsAs SK Hynix strives to maintain momentum, Samsung is not standing idly by; instead, it is fortifying its position with countermeasures of its own.

Samsung is ambitiously developing over 400 layers of 3D NAND, an initiative that reflects its ongoing commitment to innovation in the semiconductor industryRecent reports indicate that Samsung is working on its ninth-generation 286-layer 3D NAND and is simultaneously progressing towards the 400-layer technology, as disclosed in the agenda for the upcoming 2025 IEEE International Solid-State Circuits Conference.

This new 1 terabit NAND chip boasts a density of 28 Gb/mm², with over 400 layers designed in a triple-level cell configuration, marking it a significant step forward in Samsung's V-NAND technologyThe ninth generation chips employ a dual-stracked arrangement of 2 x 143 layers and support both TLC and QLC (4 bits per cell) formatsAs enticing as these advancements seem, the ninth-generation V-NAND chips promise data speeds of up to 3.2 Gbps, while the new 400-layer technology is poised to support staggering speeds of 5.6 Gbps per pin, marking a formidable increase of 75%. This miraculous leap is tailor-fit for both PCIe 5 and the anticipated PCIe 6 interconnect that promises double the speed.

Furthermore, for the development of 400-layer NAND technology, Samsung is looking into a stacked triple architecture as opposed to the existing dual-stacked design

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This transition will capitalize on Samsung's lead in layer counts since it is the only manufacturer capable of producing more than 160 layers in a single stack, while competitors have managed only up to 120-130 layersShould Samsung pursue a triple-stack approach, it could conceivably achieve an astonishing 480 layers.

Central to achieving this ambitious layer count is Samsung's "WF-Bonding" technology—specifically, wafer-to-wafer bondingThis groundbreaking technique allows separate NAND wafers embedded with manufactured units and circuits to be bonded together, optimizing manufacturing processes in terms of scalability, performance, and yield.

Samsung asserts this method will produce “ultra-high” NAND stacks with massive storage capacities and exceptional disk performance, perfect for the high-demand SSDs needed in AI data centersThe chip, dubbed bonded vertical NAND Flash or BV NAND, is touted as a "dream NAND" for AI technologies.

Since its introduction of V NAND chips in 2013, Samsung has been at the forefront of vertical storage cell technology, claiming a 1.6 times improvement in area density for its BV NAND unitsLooking ahead, the company has ambitions to introduce V11 NAND by 2027, further elevating its speed performance and achieving a 50% increase in data input and outputAdditionally, Samsung plans to offer SSD subscription services aimed at tech companies eager to manage the cost of high-investment AI semiconductor technologies.

Besides development in 400-layer NAND, Samsung intends to ramp up production capabilities of its advanced product lines next year, signaling a strong two-pronged approachPlans to install new ninth-generation (286-layer) production facilities at its Pyeongtaek campus promise a monthly output of between 30,000 and 40,000 wafersConcurrently, its Chinese factory in Xi’an will continue its transformation of the 128-layer (V6) NAND manufacturing line to a 236-layer (V8) product process.

As competitors scramble to keep pace, there is an expectation that the NAND era will reach 400 layers by 2025 and 1,000 layers by 2027. South Korean experts assert that companies like Samsung, SK Hynix, and Micron could unveil their 400-layer NAND products by 2025. As for the target of reaching 1,000-layer NAND, it remains a collective ambition among all NAND manufacturers, including Kioxia.

Micron has long set its sights on increasing NAND layers to over 400, having laid out its roadmap back in 2022. Reports have emerged indicating that Micron plans to utilize a double-stacking technique—stacking two 3D NAND chips together, known as “serial stacking.” This approach addresses semiconductor manufacturing challenges, such as etching connecting holes between layers, problematic due to increasing depth, which can deform the sides of the holes and hinder NAND functionality.

Micron has emphasized its focus on QLC (4 bits per cell) NAND, though it has refrained from discussing plans to implement PLC (5 bits per cell). Western Digital, in line with its own research endeavors, is advancing royalty-free technology to develop PLC NAND, which Solidigm is also exploring

Micron's cautious approach speaks volumes about its calculated strategy rather than an outright denial of PLC NAND’s viability.

On the other hand, Western Digital posits that slightly higher layer counts are not inherently advantageous, as it concurrently reduces unit dimensions while increasing the height through more layersThis synergy allows for chip density equivalences or surpassing competitors while maintaining fewer layers.

As companies look ahead, the ambitious target of 1,000 layers becomes an industry-wide goalKioxia recently announced ambitious plans at an international memory technology seminar held in Seoul, aiming for 1,000-layer 3D NAND by 2027. In the past, Samsung claimed that it aspires to surpass 1,000 layers of NAND technology by 2030, but achieving this milestone presents significant hurdles.

Kioxia’s projections, as reported by the Japanese media segment PC Watch, hint that this aspiration is grounded in historic trends and enhanced existing NAND cell technologiesThe company estimates that NAND chip density may reach 100 Gbit/mm² and 1,000 layers within three years, necessitating a growth rate to sustain a 1.33 times annual increase.

For Samsung, researchers at the Korea Advanced Institute of Science and Technology (KAIST) have previously presented findings on utilizing hafnium ferroelectrics as a “key driver” for achieving over 1,000-layer QLC NAND, which could stand as a watershed achievement in non-volatile storage technologyWhile Samsung does not directly participate in this research, the involved team’s alignment with Samsung raises expectations that successful breakthroughs in this area will transition to Samsung's labs.

Nevertheless, scaling up to four-digit layer counts is no simple featAs noted by storage news websites like Blocks & Files, achieving greater density with 3D NAND isn’t just about adding more layers onto a chipEach layer necessitates an exposed edge that connects storage units, creating a stair-stepped profile of the chip

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